This invention relates to a processing circuit for use in processing digital signals in a signal processor.
In general, digital signal processing can accomplish reliability and stability higher than analog signal processing and realizes a filter and a modem which have high reliability and high stability. In addition, the digital signal processing enables a time-varying adaptive filter which can not be expected in the analog signal processing.
However, the digital signal processing is inferior in a size of hardware and in power consumption to the analog signal processing. Under the circumstances, the digital signal processing has not been put into practical use until recent rapid evolution of a digital large scale integration circuit, namely, the advent of a signal processor for processing digital signals.
Such a signal processor must process arithmetic operation at a high speed because a differential and an integration can be carried out in a digital manner. The signal processor has therefore been developed independently of a general purpose computer and a general purpose microprocessor.
In order to increase throughput of the signal processor by the use of a small amount of hardware, each value or number is frequently represented by two's complement of a binary number and is often expressed by a fixed-point representation. More specifically, the signal processor processes a digital signal which is subjected to analog-to-digital conversion and which is normalized with reference to a maximum acceptable amplitude of an analog-to-digital converter. For this purpose, the maximum acceptable amplitude is represented by 1.0.
In the fixed-point representation, a fixed point is placed between a most significant bit and a most significant bit but one. Each value is handled as numerals falling within a range from -1 (inclusive) to +1 (exclusive). The range will be called a predetermined dynamic range and specified by [-1, +1). It is mentioned here that the most significant bit serves as a sign bit, as known in the art.
In an article contributed by Takao Nishitani et al to IEEE Journal of Solid State Circuits, Vol. SC-16, No. 4 (August 1981), pages 372 to 376, a signal processor is used to calculate a product of a first input data word and a second input data word. When each of the first and the second input data words has a single precision bit length of N bits given by the fixed-point representation of two's complement, the product can be represented by a double precision bit length of (2N-1) bits. In this event, a fixed point of the product is located between a most significant bit and a most significant bit but one, like each of the first and the second input data words. A more significant half (N bits) of the product is produced as an output signal so as to keep a dynamic range of each signal constant.
In a finite impulse response (FIR) filter, such a signal processor must carry out an arithmetic operation given by: ##EQU1## where x.sub.j and y.sub.j are representative of input and output signals produced at a time instant j, respectively, and a.sub.i, coefficients for deciding a characteristic of the filter. The output signal y.sub.j may be referred to as a sum signal.
In Equation (1), the coefficients a.sub.i are determined so that the output signal y.sub.j averagely falls within the predetermined range of [-1, +1), if the input signal x.sub.j is within the predetermined range. However, the coefficients a.sub.i are not always restricted within the predetermined range of [-1, +1). This means that an intermediate result of calculation of Equation (1) often falls outside of the predetermined range of [-1, +1).
Taking the above into consideration, a conventional method converts the coefficients a.sub.i into the predetermined range of [-1, +1). For this purpose, the respective coefficients a.sub.i are modified into modified coefficients b.sub.i by dividing the coefficients a.sub.i by a number which is greater than a maximum value of absolute values of the coefficients a.sub.i and which is equal to two to a K-th power. More particularly, the modified coefficients b.sub.i are given by: EQU b.sub.i =.sub.i .multidot.2.sup.-K. (2)
Under the circumstances, Equation (1) is rewritten by the use of Equation (2) into: ##EQU2##
From Equation (3), it is readily understood that the output signal y.sub.j can be calculated by accumulating products of b.sub.i and x.sub.j-i to obtain a result of accumulation and thereafter by multiplying the result of accumulation by 2.sup.K. As mentioned before, each of b.sub.i and x.sub.j-i falls within the predetermined range of [-1, +1) and the product thereof also falls within the above-mentioned range. However, on calculating a sum of the products, M in number, either an intermediate result or a final result of the calculation might fall outside of the predetermined range of [-1, +1). In other words, an overflow might occur in the course of calculation.
Each time when the overflow occurs in a signal processor comprising a single precision adder, it is usual that a maximum value is substituted for an overflow value by hardware. Alternatively, the overflow is neglected and handled as a calculation noise.
As far as the finite impulse response filter is concerned, such an overflow does not put a system in an unstable state.
However, in a system, such as an infinite impulse response filter, having a feedback loop, occurrence of an overflow gives rise to unstability of the system. Accordingly, replacement of a maximum value should be done on occurrence of the overflow even at the cost of an operation speed.
As mentioned above, conventional methods either neglect an overflow appearing in the course of calculation or replace a maximum value each time when an overflow occurs. The neglection of overflow and frequent replacement of the maximum value result in an undesirable error of the output signal Y.sub.j.
In a paper described in PROCEEDINGS ICASSP 85, IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, VOL. 1, pages 228 to 231, a signal processor is disclosed by Cole Erskine et al. The signal processor is for carrying out calculation of Equation (1) and comprises a multiplier for multiplying a first data word of 16 bits by a second data word of 16 bits to produce a product of 32 bits. Each of the first and the second data words has a single precision bit length while the product has a double precision data length. The product of 32 bits is sent through a shifter to an arithmetic/logic unit to be successively accumulated into a result of accumulation of 32 bits. The result of accumulation is divided into an upper significant half of 16 bits and a lower significant half of 16 bits which are kept in an upper part and a lower part of an accumulator, respectively. The upper and the lower significant halves of the result of accumulation are produced as an accumulator output signal from the accumulator. The accumulator output signal is fed back to the arithmetic/logic unit on one hand and are delivered to a data bus of 16 bits through shifters on the other hand. The shifters serve to adjust the accumulator output signal of 32 bits to the data bus of 16 bits by shifting the accumulator output signal by a single bit or four bits. Such shift operation may be carried out towards a least significant bit of the accumulator output signal and consequently brings about no overflow in the shifters.
At any rate, no consideration is paid to an overflow which may occur in the arithmetic/logic unit.